So it seems that silicon can't go smaller than 5nm due to leakage, it had to happen, but not to worry "molybdenum disulfide" could save the day. It's very early days and the technology has some issues to overcome but ...

Full Story:
http://arstechnica.com/science/2016/10/nanotubes-atomically-thin-material-smallest-transistor-ever/

  I remember a transistor the size of a pinhead from ages ago,  The tunnel diode that replaced a coil and capacitor used in a tank circuit so you could make a FM transmitter so small.  They would invent things the user could only dream about.
Carl2

Interesting research.

Even with current trends towards 5nm (Kaby Lake is 14nm), processors are still 1 layer. Most desktop processors are more powerful than most people need most of the time. Low power or more MIPS per Watt seems to be the best trend for now.

What will be the next game changer? Carbon nanotubes, Graphene or multi layers?

Been doing a little maths and each generation seems about 63-71% of the previous generation.

That makes the next generation about 9-10nm followed by 6-7nm. Here's the comparison wiki. And all of 'em here.

The 1st Pentium was 800nm from 1993 and the 1st 8086 (16bit) was 3000nm from 1978 with their 1st processor 4004 (4bit) was 10000nm from 1971

The 1st one I owned was a 80386 (32bit) at 1000nm from 1992 (the 33MHz version).

We've come a long way but there's plenty of room at the bottom. (I'm miss quoting someone)

"processors are still 1 layer"
I had read this and possibly we are taking about different things, I'm not sure what you mean when you say one layer.  I'll try to explain what I am thinking of by mentioning the field effect transistor,  a transistor that uses a gate rather than the junction caused by using different doping to form the collector, base and emitter.  So the FET uses a gate rather that changes current flow by providing a potential or voltage to change current flow.  I actually forgot the name of the different parts, source, gate and another one.  The Fet is made by depositing a layer of one material, that is covered with an insulator, the gate material is deposited, so we have three layers of material so far and the Fet is still not finished.   When I speak of a layer this is what I mean could you explain what you mean by one layer please.
Carl2

The last leg you are looking for is 'Drain'. Most chips use FET rather than bipolar transistors. Some power transistors are MOSFET and can be very sensitive to static discharge.

What I mean by 1 layer is all the transistors are made on one plain. They are not stacked on top of each other. If they were stacked, you could fit more on per die size. Manufacturing would be more difficult and power dissipation would probably be an issue.

HP patented the circuitry for multi layered (stacked) chips a few years back when they were developing their memristor technology.

  I remembered the drain after I posted this but not sure.  I'm not sure if you are saying they are using dies because I thought they were using wafers containing all the circuity need for a cpu.  I had worked for a company that made special circuity using dies, this was before the personal computer.  I remember the transition from ttl logic to cmos logic, never had a problem with them.  Anyways I'm thinking Intel that made the first micro processor has enough capabilities to make wafers for the processor.
Carl2