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Integrated CMOS Tri-Gate Transistors

Started by Data, June 11, 2011, 14:40:49 PM

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Snowcrash, have you seen this?

Read it, then please give a breakdown of what it means to us.  ;D

Integrated CMOS Tri-Gate Transistors


Not in the mood for reading all that but have heard about this on a podcast I was listening to recently.

When they scale down a chip they are scaling the x-y axis. The thickness stays about the same; the z axis.
Things are getting so small the surface area of the gate (the bit that controls a transistor) is causing problems with efficiency.
Intel have extruded the gate in the z axis to give it more surface area. In doing so they have also gained efficiency with lower power and faster speeds (more of one, less of the other) even without going down a size, which they have also done. I think the new generation they are working on will be 22nm (32nm current Sandy Bridge).
The next gereration is to be called Ivy Bridge and is based on Sandy Bridge but 22nm and tri-gate.

I'm still not sure about the graphics procesing on chip. It only seems to be any use if you don't run a graphics card. It is reported to be more efficient with low end graphics than the graphics card but both run no matter what so you don't get ant power savings. Plus they are problematic switching between. They seem to be a technology not working right as yet.
"I cannot remember the books I've read any more than the meals I have eaten; even so, they have made me."

Ralph Waldo Emerson


I thought it was something like that, thanks for explaining.

I'm glad Intel have found a way to take chip technology to the next level, for a moment there it seemed they had hit a wall, but as usual they find another method.

Things are looking good for a year or two then.

Will probably skip Sandy Bridge and go to Ivy Bridge for my next build.   


Here's a nice little video about Intel's 3D Tri-gate technology.